Radio silence and gouging (A follow-up to Black Piday)

It seems that the raspberrypi.org forums are back up, and have been for 12 hours or so.  So far, there's only 2 people on the forums who seem to have got confirmed orders for Pis from the first batch.  Given that there were upwards of 12K people registered on the forum, and most of them were probably frantically trying to get orders in from 06:01 on the 1st, we can safely say that demand was "underestimated".

Oddly, there seems to be very little spleen being vented towards the Foundation, but some not inconsiderable anger directed at Farnell and RS, mainly over their incompetent and inconsistent handling of ordering and preordering.  This anger is, I believe, misplaced - there's far more wrong with what RS (to a lesser extent) and Farnell are doing than being simply incompetent.

I'll say it now.  I feel that handing over control to Farnell and RS was a massive mistake, and it may cost the foundation much of the goodwill they have accumulated even whilst they were missing their hoped-for delivery dates.

RS are seemingly not acknowledging anything.  Nobody is reporting any response at all from them.  "Register interest" and - nothing, nada, que chi.

Farnell are, logistically speaking, doing better - they (if you can find the link to order in your country) are accepting preorders.  However, they are:

• Giving wildly optimistic delivery dates on order, which are then being modified in email
• Advertising and confirming orders at one price, and then subsequently modifying the price (which, as far as I understand it, but IANAL, is contrary to the Sale of Goods Act, at least in the UK)
• Selling the Pi at inflated prices.  This is the worst, as the price point was the one thing the Foundation have stuck to, and was a major selling point. The Model B (which is all that's on "sale" at the moment) was supposed to be 35 USD plus locally applicable taxes.  In France (and, I believe, the rest of Europe), Farnell are quoting 33.07 EUR before tax, which comes to 42.65 USD.  That's a 21% markup.  The UK gets an advertised 24.65 GBP, or 39.03 USD, but a reportedly subsequently modified price of 26.65 GBP, or 42.20 USD.  Again, a >20% markup.

I cannot understand why the Foundation are allowing this.  RS are advertising at 21.60 GBP, which is, at least, at the 35 USD price point.

Farnell are destroying the Foundation's year-long commitment to a given price point.  The Foundation should pull their licence NOW.

It has been pointed out that, in their defence, Farnell are merely rolling the shipping cost into the purchase price and shipping for free, but that's actually fairly dishonest - it's a "reverse eBay" (i.e. the reverse of the situation where an article is listed with a low price and then the rest is made up by gouging the shipping).  If you were (able) to order more Pis than one, you effectively pay for single item shipping on each and every one (or, put simply, overpay your shipping cost massively).

Black Piday

So, I didn't get a Raspberry Pi.  I'm not feeling overly bitter about it, as I wasn't actually expecting to, if nothing else because I was already at work before the 6AM GMT deadline. What I am mildly miffed about is that I can't currently do anything other than "express an interest in buying one" (or, in supplier-speak, "become a mailing list asset") from the major suppliers.  I've had an interest since May last year.

As I type this, the Raspberry Pi site is still showing a static page.  There's no official news about what happened, who got one, who didn't, what the details of the deal with Farnell and RS are, apart from Twitter.  The unofficial news (i.e. the stuff in print) is almost all wrong in fundamental details.

I wouldn't want to have been one of the inhabitants of #1 Fruity Loop recently. It was becoming increasingly evident that there was no way 10,000 Pis were going to suffice.  With every hour, new "news sites" were picking up on the Pi as a "$25 computer that does XBMC". None of them were picking up on the actual goal of the Pi itself, or mentioning the limitations of the Pi as an XBMC machine, or even any of the actual hardware features of the Pi beyond "it does XBMC". The wave upon wave of new users descending on the Pi forums and asking if they can install Windows on the Pi bore witness to this. What had started as a dream was rapidly becoming a monster. It was totally out of control, and there was no way the foundation would ever be able to meet the demand.  Hence, I guess, the throwing up of hands and handing control of the hardware delivery side of things to a pair of corporate rapists[1]

When people start realising what the limitations of the Pi as an XBMC machine is, the nerd rage will be spectacular.  We probably have a week or so before they start being delivered to homes around the globe, and the "this thing's a fucking pile of shit" threads on the already overloaded forums start sprouting up by the thousand.

The foundation themselves are largely to blame for this turn of events, as recent news has all been about multimedia and XBMC, and nothing to do with education at all.  Indeed, the "About Us" page on the Raspberry Pi site has been changed from a short and sweet statement of the goals of the foundation into a bunch of word salad.  From being about teaching programming, it's suddenly become

We want owning a truly personal computer to be normal for children.

So, when 6AM GMT ran around, Farnell, RS and Raspberry Pi.org went down simultaneously. Not taken down by wave upon wave of pent up demand for educational computers, but by scalpers and people from hotukdeals.co.uk. These are not people who are going to do educational projects with the board, they are going to stick them to the back of the telly with blu-tac. the foundation wanted "the community" to take the board and supplied software, run with it, and create interesting projects.  Installing XBMC is no more interesting in terms of computer science than editing a document in Microsoft Word, the kind of crap that's being taught in ICT, the kind of thing the Raspberry Pi was suposed to fix.

None of the people I know who are planning educational projects managed to get one from the first batch. Only one of them managed to get a preorder rather than "expressing an interest".

There are probably less than a hundred people on the forums who are planning interesting stuff.  putting aside 1% of the first batch "for them", even if it was done behind the scenes, would have done far more for the foundation's erstwhile goals than selling a million Pis to people who want to make Mame machines and set top boxes.

So, like I said, I'm not bitter.  But I am fucking angry.  The emphasis has gone from producing something important, i.e. a machine that helps in teaching kids (and adults) how to actually control the hardware they own, on to simply producing another gadget.  That emphasis has been changing slowly since around December.  The sale itself was a total fucking mess, and, it appears, fucked up by both the foundation (setting a solid date and time for server meltdown, days in advance, and thus further engorging the until-then self-sustaining hype machine, was never gonna be a good idea), and RS/Farnell, by all accounts, don't appear to have been even close to ready (from denying the existence of the Pi through to stating that they will only be available to resellers).

I remain totally committed to the originally stated goals of the foundation.  The ones that don't appear on the site any more.  I truly believe the Pi could change the nature of computing in a way that no other computer has ever done, that it could make an understanding of computer science part of basic education.  Indeed, even if the foundation had never managed to get a single board out of the door, it has highlighted fundamental issues in education today, raised questions, and shown that, with a bit of will, something can be done.

But all that is being lost, being driven into obscurity by a botched sale of millions of cheap, credit card sized computers running XBMC.

Badly.

I hope the foundation people at least get to pay off their personal loans, but I assume Farnell and RS are taking a substantial cut of the already slim margins.

[1] Arguably, the handing over of sales to people like RS and Farnell should have happened around December, when the beta boards landed.  At that point, the hype was containable. But that's with hindsight, and I guess at that point the foundation guys and girls still wanted to (and believe they could) keep control, which is understandable.

CAR, CDR, CONS - an aside

Commenter pcpete has been following the ARM OS stuff, but was having some trouble with my CAR/CDR/etc macros.  I figured I'd do a little writeup for those who aren't totally au fait with what that's all about.


CAR, CDR and CONS are terminology which has stuck around since the '50s.  It's not going away, so if you want to Lisp, you need to get used to it.


The original Lisp was implemented on the IBM 704 computer.  This was a machine which had a 36 bit word (peculiar, but useful) and a 15 bit address bus. 36 bit words could be split into 4 parts (and hardware support was provided for doing so) known as the address (a 15 bit value), the decrement (again, 15 bits), the tag (3 bits) and the flags (3 bits).  The very earliest work on Lisp provided operators to extract these 4 parts (Contents of Address part of Register or CAR,  and likewise for Decrement, Tag and Flags, providing CDR, CTR and CFR).  Later work (before the first implementation of Lisp) dropped direct manipulation of flags and tag, leaving CAR and CDR, and a "Construct" operator, CONS, which took values for the address and decrement parts respectively and stuffed them into a machine word.

The fact that a machine word was bigger than the size of the address of a machine word meant that it was possible to implement pairs of values and singly linked list cells within one machine word.  A pair of values (for example, 1 & 2) could be created as follows:

CONS(1, 2)

and singly linked lists by treating the 'address' part (paradoxically enough) as a value, and the 'decrement' part as the address of the next cell in the list.  By setting the last pointer to some easily-recognised value (known as 'nil'), it is possible to find the end of a list.  Thus, creating a list containing the numbers 1, 2 and 3, looks like this:


CONS(1, CONS(2, CONS(3, nil)))

Binary trees are also easy to construct using pairs - for example:

CONS(CONS(1, 2), CONS(3, 4))


I'm generally the last one to point people at Wikipedia, but there's a reasonable and rather more graphical explanation of what have become known as 'cons cells' over there. 


It's worth noting that Lisp also allows you to use the notation 'first' and 'rest' instead of 'car' and 'cdr', although this only really makes sense when in list context, and doesn't allow for composition (caar, cadr, cdar, etc).  Pretty much nobody uses first and rest.


So, Lisp uses what is, in effect, a pair (or list) oriented memory model as opposed to the more usual (these days) approach of addressing single memory cells individually.  And if one is implementing a Lisp (as I am), it makes a certain amount of sense for the low level memory allocation and manipulation functions to operate in this way.  Unfortunately, "modern" machines in general don't have words that are larger than their address bus size, and ARM is no exception to this.  ARM is a 32 bit machine - we could restrict addressing within our lisp to 16 bits (maximum 64Kwords or 256KB) and all values to 16 bits, or, more sensibly, use "virtual" words of 2 machine words (or maybe more) in size.  Usefully, ARM has LDRD (Load Register Dual) and STRD (Store Register Dual) operands that make this a snip to do.


So, we can define cons cells as 8-byte aligned pairs of 32-bit values, manipulate them as pairs using LDRD/STRD, and we're a long way towards implementing a Lisp.  


But what of the Flags and Tag stuff that was originally in Lisp?  Although, by the time Lisp came out, you had no way of directly manipulating them, they were still used to differentiate between pointers, direct values, and constants, amongst other things.  And this is something we need to be able to do as well, otherwise we can't tell if (for example) the value 0x00000000 in the CDR of a cell is a pointer to a cell at the address 0x00000000, the integer value zero, or some special value indicating nil/end of list.


As it happens, all is well. LDRD/STRD require an 8-byte aligned address, which means the low 3 bits of a pointer will *always* be 0.  We can, therefore, use those 3 bits as flags to indicate various other types, and, if we're careful, we can encode the majority of types in such a way as to keep their values "boxed" (i.e. containable in a 32 bit value).  Values requiring more than 32 bits to encode (strings, large numbers, rational numbers, etc) can either be encoded as lists of boxed values, pairs, or using any other encoding the programmer deems useful as long as they are easily recognisable.


So, back to the code I posted, which uses CAR, CDR, SET_CAR and SET_CDR macros.



/* linked list structure */
typedef struct task_list {
  task_t * _car;
  struct task_list * _cdr;
} task_list_t;


/* some LISPy primitives */
#define CAR(x) (x)->_car
#define CDR(x) (x)->_cdr

#define SET_CAR(x,y) CAR(x)=(y)

#define SET_CDR(x,y) CDR(x)=(y)


As we can see, task_list_t is an analogue for the cons cell, being simply 2 address-bus sized values held together.  Indeed, my code elsewhere looks like this:


typedef cons_t task_list_t;

but the original formulation is perhaps easier to grok at first.


So, given a pointer x to a cons cell c, we can see that CAR(x) expands to(x)->_car, in other words returning the _car element of the cell c pointed to by x.  Likewise SET_CAR(x, y) becomes (x)->_car = (y), assigning the value y to the _car element of the cell c pointed to by x. Doing this as macros is probably premature optimisation, but it's "the done thing".


Our task scheduler uses a list (actually, a plurality of lists) of tasks to execute, and considers them for execution in a "round robin" style.  So, assuming we have 4 tasks, a, b, c and d, we might have a list that looks, in lisp syntax, like this:


(a b c d)


or, in diagram form, where the top row is the CDR of the cell, and the bottom the CAR, and * indicates a pointer to the next cell


* - * - * - nil
|   |   |   |
a   b   c   d


We need to rotate the list as we consider each task, so that the next time through we consider the next task. So after considering task a for execution, we want the list to look like this:


(b c d a)



or, in diagram form


* - * - * - nil
|   |   |   |
b   c   d   a

In true lisp style, we'll use a singly linked list for this, with the CAR of each cell being a pointer to the task, and the CDR being a pointer to the next cell, or nil for end of list.  


So, we come in, and we find the CAR and CDR of the (original) list.  CAR is, obviously enough, task 'a', the task we want to consider for execution.  CDR, however, is not task b, but the rest of the list (hence the alternative 'rest' in Lisp) - i.e.


(b c d)



or, in diagram form


* - * - nil
|   |   |
b   c   d

So our next step is to put 'a' onto the end of the list.  This is not as simple as it seems - CONS can only be used to push items onto the front of a list - CONS(list, a) would result in this:


((bcd) . a)



or, in diagram form


a
|
* - * - nil
|   |   |
b   c   d

which is not a true list in Lisp terms (it's a "dotted pair" with a list as its first element). We need some sort of APPEND operator that adds an element to the end of a list, a sort of 'reverse cons'.  Lisp has one of those, it's (oddly enough) called APPEND, it's usually defined recursively, and it always creates new cons cells all over the place.  We really don't want to go allocating new memory in a function that's going to be called thousands of times per second simply to move a few values about - we want to keep the same cons cells and simply swap their CDR values around.  The algorithm thus becomes:


first := list
if CDR(first) != NIL
  list, end := CDR(first)
  end := CDR(end) while CDR(end) != NIL
  SET_CDR(first, NIL)
  SET_CDR(end, first)


With that in mind, have another read through http://stm8sdiscovery.blogspot.com/2011/12/developing-multitasking-os-for-arm-part_14.html


Simon

Developing a multitasking OS for ARM part 3 3/4

So, we looked at how to do the difficult part of task swapping last time, now let's look at how we go about handling interrupts and the syscall layer.

Firstly, interrupts.  We'll not bother with FIQs for the moment, we'll stick with IRQs.

Despite having an ARM1176 core, the Raspberry Pi (or, rather, its Broadcom SoC) doesn't have a vectored interrupt controller - instead it has 3 "standard" ARM interrupt controllers.  That makes things a bit more complex for interrupt handling, but it's not too arduous.  As a quick reminder, here's the IRQ code we had before, with a little bit of meat in the middle:

.global _irq_handler

_irq_handler:
sub lr, lr, #4 /* Save adjusted LR_IRQ */
srsdb sp!, #SYS_MODE /* save LR_irq and SPSR_irq to system mode stack */

cpsid i,#SYS_MODE /* Go to system mode */

push {r0-r12} /* Save registers */

and r0, sp, #4 /* align the stack and save adjustment with LR_user */
sub sp, sp, r0
push {r0, lr}

/* Identify and clear interrupt source */
/* Should return handler address in r0 */
bl identify_and_clear_irq

blxne r0 /* go handle our interrupt if we have a handler */
/* An interruptible handler should disable / enable irqs */


/* Exit is via context switcher */
b switch_context_do

and the context switcher looks like this:

.global switch_context_do

switch_context_do:

/* Do we need to switch context? */

mov r3, #0x0c /* offset to fourth word of task block */

ldr r0, =__current_task

ldr r1, [r0]

ldr r0, =__next_task

ldr r2, [r0]

cmp r2, #0 /* If there's no next task, we can't switch */

beq .Lswitch_context_exit

cmp r1, #0 /* In the normal case, we will have a __current_task */

bne .Lnormal_case

/* When we get here, we're either idling in system mode at startup, or we've */

/* just voluntarily terminated a task.  In either case, we need to remove the */

/* return information we just pushed onto the stack, as we're never, ever going */

/* back. */

pop {r0, r1} /* remove any potential stack alignment */

add sp, sp, r0

add sp, sp, #0x3c /* and the other registers that should be there */

/* r0-r12, interrupted pc & spsr */

/* Now we can do our first actual task swap */

ldr r0,  =__next_task /* swap out the task */

ldr r2,  [r0]

ldr r0,  =__current_task

str r2,  [r0]

ldr sp,  [r2, r3] /* and restore stack pointer */

b .Lswitch_context_exit /* bail */

.Lnormal_case:

cmp r1, r2 /* otherwise, compare current task to next */

beq .Lswitch_context_exit

clrex /* Clear all mutexes */

/* At this point we have everything we need on the sysmode (user) stack */

/* {stack adjust, lr}_user, {r0-r12}_user, {SPSR, LR}_irq */

/* Save our stack pointer, and swap in the new one before returning */

ldr r0, =__current_task /* save current stack pointer */

ldr r0, [r0]

str sp, [r0, r3] /* stack pointer is second word of task object */

ldr r0,  =__next_task /* swap out the task */

ldr r2,  [r0]

ldr r0,  =__current_task

str r2,  [r0]

ldr sp,  [r2, r3] /* and restore stack pointer */

.Lswitch_context_exit:

pop {r0, lr} /* restore LR_user and readjust stack */

add sp, sp, r0

pop {r0-r12} /* and other registers */

rfeia sp! /* before returning */

The context switcher looks complex, but it isn't really.  There's 4 cases to cater for, viz:

• No 'next' task, don't switch
• No 'current' task, switch to 'next' task, cleanup stack and switch to 'next' task
• 'next' task is the same as 'current' task, don't switch
• 'next' task is different from 'current' task, switch

Obviously, the meat of the interrupt handler is held in 'identify_and_clear_interrupt', which does pretty much what it says on the tin.  In this article, I'll show the handler for the qemu platform, which is significantly simpler than that for the Pi, but the Pi handler looks largely the same modulo having to deal with 3 controllers.

.global identify_and_clear_irq

identify_and_clear_irq:

FUNC identify_and_clear_irq

ldr r4, =.Lirq_base

ldr r4, [r4]

/* read the vector address to indicate we're handling the interrupt */

ldr r0, [r4, #IRQ_HANDLER]

/* which IRQs are asserted? */

ldr r0, [r4, #IRQ_STATUS]

ldr r5, =__irq_handlers

clz r6, r0 /* which IRQ was asserted? */

mov r1, #1 /* make a mask */

bic r0, r0, r1, lsl r6 /* clear flag */

str r0, [r4, #IRQ_ACK] /* Now acknowledge the interrupt */

str r0, [r4, #IRQ_SOFTCLEAR] /* and make sure we clear software irqs too */

ldr r0, [r5, r6, lsl #2] /* load handler address */

.Lret: bx lr /* exit */

.Lirq_base:

.word IRQ_BASE

.bss

.global __irq_handlers

__irq_handlers: .skip 32 * 4

and patching in a hander is as simple as setting the address for the interrupt handler into __irq_handlers at the appropriate place.  Simples, as they say in internet-land.

Syscalls are very similar.  Here's the syscall handler:

.global _svc_handler

_svc_handler:

srsdb sp!, #SYS_MODE /* save LR_svc and SPSR_svc to sys mode stack */

cpsid i,#SYS_MODE

push {r0-r12} /* Save registers */

and r0, sp, #4 /* align the stack and save adjustment with LR_user */

sub sp, sp, r0

push {r0, lr}

ldr r0,[lr,#-4] /* Calculate address of SVC instruction */

/* and load it into R0. */

and r0,r0,#0x000000ff /* Mask off top 24 bits of instruction */

/* to give SVC number. */

ldr r2, =__syscall_table /* get the syscall */

ldr r3, [r2, r0, lsl#2]

cmp r3, #0

beq _syscall_exit

tst r3, #0x01 /* what linkage are we using */

bxeq r3 /* ASM, just run away */

bic r3, r3, #0x01

blx r3 /* C, must come back here */

.global _syscall_exit

_syscall_exit:

pop {r0, lr} /* restore LR_user and readjust stack */

add sp, sp, r0

pop {r0-r12} /* and other registers */

rfeia sp! /* before returning */

.section .bss

.global __syscall_table

__syscall_table:

/* leave space for 256 syscall addresses */

.skip 2048

The fun bit is how we go about getting the syscall number into the handler.  I've taken the "canonical" approach of using the svc operand, hence the bit where we get the instruction and extract the number.  Other ways include using a register, a global variable, pushing onto the stack, or some combination of these.

The other twist here is that I allow for both C and assembler syscall functions by setting (or not) bit 0 of the function address in the syscall table.  Assembler syscall handlers must, of course, exit via _syscall_exit or equivalent, but that's down to the programmer to get it right.

Developing a multitasking OS for ARM part 3 1/2

Okay, so last time we looked at what we need to schedule and store top level information about tasks in our fledgling OS.  And it was pretty easy to do, because we could do all of it in C.  Unfortunately, things are about to get complicated again, because we're about to dive down into assembler again.

Whoopee!  I can almost hear the sound of "back" buttons being clicked as I type this.

So.  Multitasking.  How's that gonna work, then?  Largely speaking, there's 2 types of multitasking - preemptive multitasking, where tasks run for a specified amount of time then get forcibly swapped out, and cooperative multitasking, where tasks run until they decide to give some time to someone else.  We're going to implement (because there's precious little overhead in doing so) a hybrid where tasks can be "nice" and give time to others, but where the absolute maximum time they get is capped by a preemptive scheduler.

So.  Let's look at the sequence of events for a user-triggered task swap.  We want the user to use a line of code that looks like this (remember, I'm developing something that runs scheme...)

(task-swap-out)

However, the user's code is running in user mode (remember the ARM processor states), and it can't directly access the task scheduler.  This is where software interrupts / SVC calls come in - the user's code *can* use the svc instruction.  This, in fact, is the beginning of what is known as a syscall interface, the way that unprivileged user code calls (or causes to happen) kernel functions.

Executing the svc instruction causes the following to happen:

• CPSR_usr is transferred to SPSR_svc
• PC is stored in LR_svc
• Processor switches to SVC mode (SP_usr and LR_usr are now hidden by SP_svc and LR_svc, CPSR is identical except for processor state change)
• PC is loaded with the address of the SVC exception handler

At this point, what we need to do is store R0-R12, LR_usr and PC (before entry to svc handler) into the user stack, in a known order, then save the user stack pointer to the task's "housekeeping" information, load the equivalents back in for the next task, and jump out of the handler back to user code.  We'll get onto that in a minute.

Preemptive task swapping will be done by using a timer interrupt.  Thus, for a preemptive task swap, the situation is quasi-identical, with _svc above replaced by _irq.  The only difference is that the PC stored to LR_svc is actually 4 bytes on from where we want to restart, so we need to remember to take that into account.

So.  How do we go about saving our information to the user stack?  This is made quite easy by the fact the user mode register are identical to the system mode registers.  So we need to save the svc/irq mode stuff (LR, SPSR) into the system mode stack, then swap into system mode and save the rest.  The first bit is covered by one instruction, which might have been made for the task:

srs (Store Return State) - store LR and SPSR of the current mode onto the stack of a specified mode


and, of course, its "twin"


rfe (Return From Exception) - load PC and CPSR from address

So, the preamble for the svc handler is as follows:


FUNC _svc_handler
srsdb sp!, #SYS_MODE /* save LR_svc and SPSR_svc to svc mode stack */
cpsid i,#SYS_MODE     /* go sys mode, interrupts disabled */

push {r0-r12} /* Save registers */


and r0, sp, #4 /* align the stack and save adjustment with LR_user */
sub sp, sp, r0
push {r0, lr}

and for an irq:

FUNC _irq_handler

sub lr, lr, #4 /* Save adjusted LR_IRQ */

srsdb sp!, #SYS_MODE /* save LR_irq and SPSR_irq to system mode stack */

cpsid i,#SYS_MODE /* Go to system mode */

push {r0-r12} /* Save registers */

and r0, sp, #4 /* align the stack and save adjustment with LR_user */

sub sp, sp, r0

push {r0, lr}

Note that the only difference is that the irq handler adjusts the return address (as we want to go back to the interrupted instruction, not the next one).

Given that we are now *always* in system mode, exiting from either handler is identical:

pop {r0, lr} /* restore LR_user and readjust stack */

add sp, sp, r0

pop {r0-r12} /* and other registers */

rfeia sp! /* before returning */

I'll move onto how to implement the guts of the two handlers in the next post.  But before we go, here's how we set up a task in "C" land.

Remember, when we switch into a task, we will be pulling a stored process state from the task's stack into the registers, and then restoring the PC and CPSR, also from the task's stack.  Setting up a task, then, involves "faking" the preamble of the exception handlers above.  Note the use of exit_fn as the value of LR_usr, this is where we go when a task dies, and is used to clean up after task exit, and the use of 'entry' (the address of the task's entry function) as the value of LR_svc/irq, which will be used as the "return" address from the exception handler.

The use of exit_fn means we can schedule "one-shot" tasks (which not all realtime OSs can do).  Hooray for us.

  // Allocate stack space and the actual object

  task_t * task = malloc( sizeof(task_t) );

  void * stack = malloc( stack_size * 4 );

  unsigned int * sp = stack + stack_size;

  task->stack_top = stack;

  task->priority = priority;

  task->state = TASK_SLEEP;

  task->id = (unsigned int)task & 0x3fffffff;

  

  *(--sp) = 0x00000010;             // CPSR (user mode with interrupts enabled)

  *(--sp) = (unsigned int)entry;  // 'return' address (i.e. where we come in)

  *(--sp) = 0x0c0c0c0c;             // r12

  *(--sp) = 0x0b0b0b0b;             // r11

  *(--sp) = 0x0a0a0a0a;             // r10

  *(--sp) = 0x09090909;             // r9

  *(--sp) = 0x08080808;             // r8

  *(--sp) = 0x07070707;             // r7

  *(--sp) = 0x06060606;             // r6

  *(--sp) = 0x05050505;             // r5

  *(--sp) = 0x04040404;             // r4

  *(--sp) = 0x03030303;             // r3

  *(--sp) = 0x02020202;             // r2

  *(--sp) = 0x01010101;             // r1

  *(--sp) = (unsigned int) env;     // r0, i.e. arg to entry function

  if ((unsigned int)sp & 0x07) {

    *(--sp) = 0xdeadc0de;           // Stack filler

    *(--sp) = (unsigned int)exit_fn;              // lr, where we go on exit

    *(--sp) = 0x00000004;           // Stack Adjust

  } else {

    *(--sp) = (unsigned int)exit_fn;              // lr, where we go on exit

    *(--sp) = 0x00000000;           // Stack Adjust

  }

  

  task->stack_pointer = sp;

Developing a multitasking OS for ARM part 3

Okay.  We're almost done with the big bits of scary assembler.  Indeed, this post is almost totally assembler free, and will deal with some C functions and definitions we need for later.

We want to do something useful with what we have at the moment.  We could simply implement "something useful" as a C language routine called c_entry(), which would run in SVC mode with interrupts off. In some cases, that would be sufficient.  But it would hardly count as an OS, let alone a multitasking one.

So, let's look at what we want to do, make some definitions.  We want tasks that run in an unprivileged mode (i.e user mode) and are either preemptively swapped out by the OS in order to run another task, or which periodically yield control of the processor to another task.  They must be able to terminate.  For the moment, we won't worry too much about protected memory spaces, IPC, or any of that jazz (which complicate matters, but which will come later).

A task, must have its own, inviolate, set of registers, and its own stack.  It must also have some other information - entry point, state, and potentially priority.  My implementation is based on scheme, so a task must also have an environment, but that's not absolutely necessary.

/* function pointer type returning void and taking a pointer to an environment */
typedef void(*task_entry_point_t)(void * environment);


/* potential task states */
typedef enum {
  TASK_RUNNABLE,
  TASK_SLEEPING,
} task_state_t;


/* And the task itself */
typedef struct {
  void * stack_top;     /* limit of the task stack */
  void * stack_pointer; /* current stack pointer   */
  uint32_t priority:5;  /* priority, 0-31          */
  uint32_t state:1;     /* state, task_state_t     */
  uint32_t id:26;       /* task id                 */
} task_t;

Obviously, we need to know what the current task is, and have a list of other tasks that might want to run.  This is not identical to my code, as tasks are actually scheme objects, but you get the idea.

/* linked list structure */
typedef struct task_list {
  task_t * _car;
  struct task_list * _cdr;
} task_list_t;


/* some LISPy primitives */
#define CAR(x) (x)->_car
#define CDR(x) (x)->_cdr

#define SET_CAR(x,y) CAR(x)=(y)

#define SET_CDR(x,y) CDR(x)=(y)

/* We'll need these later */

#define nil  (task_list_t*)0

#define skip (task_t*)0

/* And the bits we need for the actual lists */
task_t * __current_task;
task_list_t * __priority_lists[31];


Now, the approach we'll be taking to multitasking is this:
Each task is created with a prority, and positioned as such in one of the priority lists.  Every time we need to find a task, we go through the priority lists, starting at zero, and ending at 31.  We look at each element in turn of the list by removing it from the head of the list and then grafting it onto the end of the list.  This way we round-robin schedule within each priority.  Only "runnable" tasks get scheduled, obviously.  If the task is actually the placeholder "skip", we will skip onto the next lowest priority. This way, all tasks eventually get a bite of CPU, with high priority tasks getting vastly more than the low priority ones.


Obviously, the initial setup of the lists is critical, and should be done in c_entry:


task_t * __sleep_task;


for (int i = 0; i < 31; i++) {
  __priority_lists[i] = (task_list_t *)malloc(sizeof(task_list_t));
  SET_CAR(__priority_lists[i], skip);
  SET_CDR(__priority_lists[i], nil);
}

__priority_lists[31] = (task_list_t *)malloc(sizeof(task_list_t));
SET_CAR(__priority_lists[31], __sleep_task);
SET_CDR(__priority_lists[31], nil);



The astute amongst you will notice the use of the C library function malloc() in there, despite not having a c library.  Don't worry about it.  It'll come later. Do worry about me not checking for errors :)


Note that priority 31 has *no* 'skip' entry, and points to a real task.  This task should not, under any circumstances, be missed out.


Now that's all done, we can find the next runnable task.


/* lispish function */
task_list_t * nconc(task_list_t * car, task_list_t * cdr) {
  if (car == nil) {
    return cdr;
  } else {
    task_list_t * x = car;
    while (CAR(x) != nil) x = CAR(x);
    SET_CDR(x, cdr);
    return car;
  }
}


task_t * next_runnable_task() {
  for (int i = 0; i < 32; i++) {
    while(CAR(__priority_lists[i] != skip)) {
      /* rotate the list */
      task_list_t * car = CAR(__priority_lists[i]);
      task_list_t * cdr = CDR(__priority_lists[i]);
      SET_CDR(car, nil);
      __priority_lists[i] = nconc(cdr, car);
      /* check runnability */
      if (car->_car->state == TASK_RUNNABLE)
        return car->_car;
    }
  }
  /* we should never get here, but just in case, eh? */
  return __sleep_task;
}


Now, that's all fine and well, but what about setting up tasks and actually making them swap?  Ah.  That's a bit more complex, and we're gonna have to delve down into assembler again.  I'll get into that next time round.


Until then, though, here's a couple of little functions we needed before.


void * malloc(size_t size) {

  extern char * __heap_top;
  extern char * __memtop;
  char * prev_heap_top = __heap_top;
  
  if (__heap_top + size > __memtop) {
    return (void *)0;
  }
  
  __heap_top += size;
  return (void *) prev_heap_top;

}


void sys_sleep() {
  for(;;){
    // ARMv6 Wait For Interrupt (WFI)
    uint32_t * reg = 0;
    __asm__ __volatile__ ("MCR p15,0,%[t],c7,c0,4" :: [t] "r" (reg));
  }
}

Developing a multitasking OS for ARM part 2

Okay, kids, gather around and we'll carry on where we left off.

Now, we have the ARM booting, jumping to a reset handler, and dropping into an endless loop.  That's a pretty good start.  But really, we'd like to do something more - well - how to put this - "more".

In order to do this, we need to have a bit more understanding about how the ARM itself works.

If we go to the ARMv7AR Architecture Reference Manual (which can be had by registering at arm.com, or by downloading a hooky copy off the internets, either approach is feasible, and one at least of which is recommended), we see, in section B1 (the System Level Programmer's Model) a certain amount of interesting reading.  Forget the "privilege" aspect for the moment, and let's skip ahead to section B1.3.

We find that the processor has 8 separate operating modes.  These are:

User Mode, System Mode, Supervisor Mode, Monitor Mode, Abort Mode, Undefined Mode, IRQ Mode, and FIQ Mode

If we look back at the set of vectors we set up earlier, a lot of these "cross over".  So when we drop into the IRQ vector, we will be in IRQ mode.  FIQ, FIQ mode.  Either of the aborts, Abort mode.  Undefined instruction, undefined mode, and so on.  What's interesting is how the machine registers are shared between modes, and particularly the fact that all but system/user modes have their own stack pointers.

Now, when the ARM starts up, it is in SVC mode.  That's the way it is, and you can't change that.  And when it starts up, no stack has been defined.  So you need to be really damned careful in the first bits of the reset code.

Stacks on the ARM grow downwards, so the best thing to do generally is to put them at the top of memory.  As such, a typical reset routine will start by finding out how much memory is available, then setting up stack pointers for each of the operating modes.  We're nothing if not typical, so let's look at how we do that.

First thing - sizing memory.  On the versatile baseboard as emulated by qemu, this is easy.  We try writing to a bit of memory, then read back - if the value is set, there's memory there, if there's not, then we are above the top of memory.  It's not quite so simple on the Pi, as trying to write outside of physical RAM will cause an exception.  However, we're going to be a bit clever, and try to kill 2 birds with one stone.

Firstly, we need to set up some big fat global variables.


.global __memtop
__memtop: .word 0x00400000 /* Start checking memory from 4MB */
.global __system_ram
__system_ram: .word 0x00000000 /* System memory in MB */
.global __heap_start
__heap_start: .word __bss_end__ /* Start of the dynamic heap */
.global __heap_top
__heap_top: .word __bss_end__ /* Current end of dynamic heap */

__bss_end__ is set up by the linker, and it would be much better of me to use that for the initial value of __memtop (rounded up to the nearest megabyte) as well.  But hey, I'm lazy.  It'll come back to bite me later, I'm sure.

Now, as the Pi causes an exception on writes outside memory, we need to patch in a handler, temporarily.  Here's the handler:

/* temporary data abort handler that sets r4 to zero */

/* this will force the "normal" check to work in the */

/* case (as, I believe, on RasPi) where access 'out  */

/* of bounds' causes a page fault                    */

temp_abort_handler:

mov r4, #0x00000000

sub lr, lr, #0x08

movs pc, lr

Note how the comment indicates I'm not absolutely sure this will work.  This is, frankly, because I'm not sure if this will work on a real Pi, and nobody wants to let me get my hands on one.  Still, let's pretend, eh?

/* This tries to work out how much memory we have available */

/* Should work on both Pi and qemu targets */

FUNC _size_memory

/* patch in temporary fault handler */

ldr r5, =.Ldaha

ldr r5, [r5]

ldr r6, [r5]

ldr r7, =temp_abort_handler

str r7, [r5] 

DMB r12

/* Try and work out how much memory we have */

ldr r0, .Lmemtop

ldr r1, .Lmem_page_size

ldr r1, [r1]

ldr r2, .Lsystem_ram

ldr r3, [r0]

.Lmem_check:

add r3, r3, #0x04

str r3, [r3] /* Try and store a value above current __memtop */

DMB r12 /* Data memory barrier, in case */

ldr r4, [r3] /* Test if it stored */

cmp r3, r4 /* Did it work? */

bne .Lmem_done

ldr r3, [r0]

add r3, r3, r1 /* Add block size onto __memtop and try again */

str r3, [r0]

b .Lmem_check

.Lmem_done:

ldr r3, [r0] /* get final memory size */

lsr r3, #0x14 /* Get number of megabytes */

str r3, [r2] /* And store it */

/* unpatch handlers */

str r6, [r5]

DMB r12

bx lr

.Lmemtop:

.extern __memtop

.word __memtop

.Lmem_page_size:

.extern __mem_page_size

.word __mem_page_size

.Lsystem_ram:

.extern __system_ram

.word __system_ram

.Ldaha:

.extern data_abort_handler_address

.word data_abort_handler_address

We see a few things here.  Firstly, how to patch in and out the handler.  Also, that I've got fed up with doing the whole .code 32; .global foo; foo: rigmarole and defined a macro called FUNC.  We also see a macro called DMB, which implements the ARMv6 Data Memory Barrier (ARMv7 has a 'dmb' instruction, to do that, we don't).  For what it's worth, these are the macros:

.macro FUNC name

.text

.code 32

.global \name

\name:

.endm

/* Data memory barrier */

/* pass in a spare register */

.macro DMB reg

mov \reg, #0

mcr p15,0,\reg,c7,c10,5 /* Data memory barrier on ARMv6 */

.endm

So, we can hopefully now find out how much memory we have, with __memtop containing the actual top of memory and __system_ram containing the number of megabytes in case it's useful to know.

So let's look at the start of _reset...

.equ MODE_BITS,   0x1F /* Bit mask for mode bits in CPSR */

.equ USR_MODE,    0x10 /* User mode */

.equ FIQ_MODE,    0x11 /* Fast Interrupt Request mode */

.equ IRQ_MODE,    0x12 /* Interrupt Request mode */

.equ SVC_MODE,    0x13 /* Supervisor mode */

.equ ABT_MODE,    0x17 /* Abort mode */

.equ UND_MODE,    0x1B /* Undefined Instruction mode */

.equ SYS_MODE,    0x1F /* System mode */

FUNC _reset

/* Do any hardware intialisation that absolutely must be done first */

/* No stack set up at this point - be careful */

ldr r0, =.Lsize_memory

ldr r0, [r0]

cmp r0, #0

blxne r0

/* Assume that at this point, __memtop and __system_ram are populated

/* Let's get on with initialising our stacks */

mrs r0, cpsr /* Original PSR value */

ldr r1, __memtop /* Top of memory */

bic r0, r0, #MODE_BITS /* Clear the mode bits */

orr r0, r0, #IRQ_MODE /* Set IRQ mode bits */

msr cpsr_c, r0 /* Change the mode */

mov sp, r1 /* End of IRQ_STACK */

/* Subtract IRQ stack size */

ldr r2, __irq_stack_size

sbc r1, r1, r2

bic    r0, r0, #MODE_BITS /* Clear the mode bits */

orr    r0, r0, #SYS_MODE /* Set SYS mode bits */

msr    cpsr_c, r0 /* Change the mode   */

mov    sp, r1 /* End of SYS_STACK  */

/* Subtract SYS stack size */

ldr r2, __sys_stack_size

sbc r1, r1, r2

bic    r0, r0, #MODE_BITS /* Clear the mode bits */

orr    r0, r0, #FIQ_MODE /* Set FIQ mode bits */

msr    cpsr_c, r0 /* Change the mode   */

mov    sp, r1 /* End of FIQ_STACK  */

/* Subtract FIQ stack size */

ldr r2, __fiq_stack_size

sbc r1, r1, r2

bic    r0, r0, #MODE_BITS /* Clear the mode bits */

orr    r0, r0, #SVC_MODE /* Set Supervisor mode bits */

msr    cpsr_c, r0 /* Change the mode */

mov    sp, r1 /* End of stack */

/* And finally subtract Kernel stack size to get final __memtop */

ldr r2, __svc_stack_size

sbc r1, r1, r2

str r1, __memtop

/*-- Leave core in SVC mode ! */

/* Zero the memory in the .bss section.  */

mov a2, #0 /* Second arg: fill value */

mov fp, a2 /* Null frame pointer */

ldr a1, .Lbss_start /* First arg: start of memory block */

ldr a3, .Lbss_end

sub a3, a3, a1 /* Third arg: length of block */

bl memset

ldr r2, .Lc_entry /* Let C coder have at initialisation */

        mov     lr, pc

        bx      r2

cpsie i /* enable irq */

cpsie f /* and fiq */

/* Initialisation done, sleep */

ldr r2, .Lsleep

        mov     lr, pc

        bx      r2

.Lbss_start: .word __bss_start__

.Lbss_end: .word __bss_end__

.Lc_entry: .word c_entry

.Lsleep: .word sys_sleep

Note the use of msr cpsr_c, rx - this is how we change mode.  We can change mode this way from any mode except user mode.  Luckily, the user mode stack pointer is shared with system mode, so we don't need to drop into user mode at all.  So we go off, find how much memory we have, then for certain of the operating modes, we set up a stack pointer.  We then use a pre-written implementation of memset() to zero out the bss section, let the 'c' code have a go at initialising its stuff via c_entry(), turn on interrupts, and go to sleep via sys_sleep().

Next up, how we go about doing useful work...